1. Field of the Invention
The present invention relates to a level conversion circuit that converts a voltage level and to a level-conversion-function-equipped logic circuit.
2. Description of the Related Art
When a logic circuit such as an inverter is formed using a semiconductor, generally a common-source amplifier circuit such as a direct coupled FET logic (DCFL) circuit is used. If the gate voltage rises in an MESFET or JFET, in which the gate is a diode, as an example of a source-grounded FET, a current will suddenly flow through the FET and there is a possibility that the FET will break down.
Consequently, to date, a variety of technologies for inserting a level conversion circuit into the stage before a logic circuit and ensuring that an excessive voltage is not applied to an FET of the logic circuit have been devised such as a level conversion circuit described in Patent Document 1, for example.
FIG. 6 is a circuit diagram of a level-conversion-function-equipped logic circuit 1P including the level conversion circuit described in Patent Document 1. The level-conversion-function-equipped logic circuit 1P includes a level conversion circuit 10P and a logic circuit 100.
The logic circuit 100 includes an EFET 101, a DFET 102 and a resistor 103. The EFET 101 is an enhancement type FET and its source is grounded. The gate of the EFET 101 serves as an input terminal of the logic circuit 100. The drain of the EFET 101 is connected to an output terminal (output voltage Vo) and is connected to the source of the DFET 102 via the resistor 103. The DFET 102 is a depletion type FET and its drain is connected to a voltage application terminal (driving voltage Vdd). The gate of the DFET 102 is connected to the drain of the EFET 101 and the output terminal.
The level conversion circuit 10P includes an EFET 11P, a diode 12P, a resistor 13P and a DFET 15P. The EFET 11P is an enhancement type FET and its drain is connected to a driving voltage application terminal (driving voltage Vdd). The anode of the diode 12P is connected to the source of the EFET 11P. The cathode of the diode 12P is connected to the ground via the resistor 13P. A connection point between the diode 12P and the resistor 13P serves as an output terminal of the level conversion circuit 10P and is connected to the input terminal of the logic circuit 100.
The DFET 15P is a depletion type FET and its drain is connected to an input terminal (input voltage Vi). The source of the DFET 15P is connected to the gate of the EFET 11P. The gate of the DFET 15P is grounded. Even if the DFET 15P is omitted, a level conversion circuit having the same function can be realized by using for example a circuit configuration in which a resistor is connected in series between the diode 12P and the output terminal.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 2009-33637